Next-Gen Physical Design

The P&R engine that includes placement, clock tree synthesis, optimization, global routing and detailed routing.


Seamless Chip Assembly

The complete, top down floorplanning and chip assembly tool provides a seamless integrated design environment.

News and Events

09/15/2015 ATopTech’s Physical Implementation Tools Certified for TSMC’s 10nm FinFET Process Read more
04/06/2015 ATopTech Collaborates with TSMC on 10nm Automatic Place and Route Design Enablement and Tool Certification Read more
10/13/2014 ATopTech Granted "Partner of the Year 2014" Award from TSMC Read more

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The solutions for your advanced technology nodes design challenges


We help designers worldwide accomplish the fastest time to design closure on advanced technology nodes

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