Apogee is a complete top down floorplanning and chip assembly tool that complements Aprisa, Atoptech's block level implementation tool. Apogee and Aprisa's shared timing, placement, and routing engines enable excellent correlation between block and top level timing, and provide a seemless integrated design enviorment for complex chip designs.

Apogee features include:

  • Virtually unlimited capacity with mutli-cpu capability
  • Automatic hierarchy partitoning with full rectilinear support
  • Fast, near-detail quality automatic macro placement
  • Support for a mix of black box and completed block netlists
  • Virtual top level timing optimization and block timing budgeting
  • Unique, on-the-fly timing and physical abstraction elimiates creating of extra files and models for blocks while drastically reducing run time and memory
  • Global router based congestion-aware pin optimization capable of handling complex rectilinear blocks and repeated block pin assignments
  • Automatic feedthrough insertion and feedthrough buffering
  • Supports push down of top level objects into blocks including custom routes and blockages
  • Block latency aware top level CTS
  • Block timing aware signal integrity fixing
  • Fast, top level optimization and router that correlate well with block level timing
  • Easy, intuitive use model for merging block projects and switching between different block views