APRISA - Next Generation Physical Design

Aprisa is a complete P&R engine including placement, clock tree synthesis, optimization, global routing and detailed routing. The core of the technology is the hierarchical database. Built upon that, there are common “analysis engines”, such as RC extraction, DRC engine, and an advanced, extremely fast timing engine to solve the complex timing issues associated with OCV, SI and MCMM analysis. Those engines support the precision optimization engine which is consistently used across every P&R step. Aprisa uses state-of-the-art multi-threading and distributed processing technology to further speed up the process and avoid the exploding runtime issues with modern nanoscale design. Because of this advanced architecture, Aprisa is able to deliver predictability and consistency throughout the flow, and hence faster total turn-around time (TAT) and best quality of results (QoR) for the physical design projects.

 

 

 Key features  Key benefits
  • Unified Architecture and hierarchical database
  • Mulit-threaded and deistrubuted engines
  • Capacity up to hundreds of millions of gates
  •  Up to 3-5X faster total turnaround time
  • Homogenous cross-level design environment
  • In-Hierarchy Optimization (iHO) for top-level timing closure
  • Easier to support hierarchical flow
  • Easier to apply hierarchical ECO
  • Faster and easier top-level timing closure without long cycle of timing re-budgeting and timing model updating
  • Adaptive MCMM Optimization for all stages in the flow
  • Optimize designs efficiently for all design corners and operational modes and for multiple design targets
  • Full utilization of available CPU’s and memory for best runtime and QoR
  • Progressive MCMM CTS
  • Skewgroup-based CTS
  • Efficiently Balanced clock trees for all modes and corners
  • Flexibility to leverage skewgroup information for even more efficient clock trees
  • Less buffers for clock trees
  • and 20% less power and area and better timing closure
  • Excellent correlation with sign-off timing, SI, extraction and DRC tools
  • SI-aware placement optimization and global route optimization
  • In-route DFM with wire spreading, metal fill and DFM via insertion
  • Signal net EM analysis and optimization
  • Less rounds of design iterations and ECO’s
  • Better quality of result (QoR)
  • Shorter overall turn-around time (TaT)
  • Power-centric optimization
  • Ensure more low leakage cells are used for best possible power
  • Full support of both UPF and CPF with Intelligent Always-On buffer insertion and built-in power-spec checker
  • Support multi-power-domain designs
  • Reduce the use of Always-On buffer for better power consumption and routability
  • Ensure power device insertion comply to the specification