Clock Tree Synthesis (CTS) and Optimization

Aprisa´s sophisticated CTS engine handles scenarios for complex designs. Optimizing for both area and leakage power, it minimizes the number of buffers. The CTS engine does optimization for skew, minimization of global, local and inter-clock skew and supports useful local skew control for overall timing optimization. In addition, the engine supports:

  • Cluster-based clock trees or meshes
  • Gated and generated clocks
  • Synchronization of generated clock pins
  • Automatic clock gate cloning and de-cloning
  • Matching of latency targets specified by user for any pins
  • Automatic creation of special routing constraints (layer, double width/spacing/via, shielding, etc.)
  • Low-Power Clock Tree Synthesis
  • Multi-corner and multi-mode clock tree synthesis and clock optimization
  • Level-balanced Clock Tree Synthesis
  • Route-based clock tree optimization

Additionally, the Clock Tree Browser GUI provides sophisticated features such as cross-probing and editing on the fly such as resizing clock buffers or moving clock buffer/leaf cell to different levels. It provides detailed delay, transition, skew and load information for each node; and can find or highlight any max or min path to calculate local skew.

Clocvk Tree Synthesis and Optimization