Complex clock distribution network
The quality of the clock distribution network, or clock tree, continues to be the limiting factor for high performance and low power for modern digital chips. The clock tree designers use various clock tree cells, such as MUX, FF and clock gates, to create complicated overlapping and inter-related clocktrees under different design modes. In addition, RC and cell variation can also cause large skews at certain design corners. The challenge of the modern clock tree synthesis (CTS) engine is to construct balanced clock trees with minimum skew in multiple design corners and functional modes.
Progressive MCMM CTS
Progressive MCMM CTS technology in Aprisa revolutionized traditional approach of CTS, which synthesize the clock tree for one mode and one clock at a time. Instead, a global view of the entire clock tree system is automatically identified for all modes. Sub-trees are constructed progressively based on their importance to all modes and all clocks. Each tree is optimized for all design corners simultaneously. Progressive MCMM CTS delivers balanced clocktrees for all modes and all corners with minimum impact to timing and power.
In today’s large digital designs, system clocks are distributed to many functional blocks. While there are stringent timing constraints within each block, the requirement for inter-block signals may not be as critical. Traditional clocktree-based CTS, which attempts to balance the entire clock tree, may lead to unnecessary over-design and wasted area and power. Aprisa’s Skewgroup-based CTS offers added flexibility to leverage skewgroup information within the clock to build more efficient clocktrees. The result is less buffers, less power, less area, and better timing closure.