Design Complexity

As the size and complexity of today’s SoC designs continue to increase, the hierarchical flow for physical implementation becomes critical. Earlier generations of P&R tools were created for flat P&R methodology. Separate top-level hierarchical engines were later developed for the top-level floor-planning and chip-assembly. This retro-fit hierarchical flow is difficult to maintain and less flexible for top-level timing closure.

Homogenous cross-level design environment

Apogee/Aprisa technology is architected and optimized purposely for hierarchical flow. It is built on a unified hierarchical data model, which retains hierarchical information throughout the P&R design process. This unified database and the common service engines allow easy transition between top-level and block-level tasks. Hierarchical ECO can also be supported effortlessly.

in-Hierarchy Optimization (iHO) for top-level timing closure

in-Hierarchy Optimization (iHO) is a unique capability in the Apogee to enable fast top-level timing closure. It allows block-level optimization directly within Apogee top-level hierarchical engine, with the availability of detail block P&R data and top-level timing information. iHO offers the simplest and the most effective way to close difficult top-level timing, without tedious timing re-budgeting and timing model updates.