Low power designs
The progress in portable electronics continues to demand advanced methods, such as multiple voltage domain, multiple-Vt cells, power gating and clock gating, for more power efficiency. Those techniques require the efficient support in the P&R tools to meet the power specification.
Extreme power specification can only be met when low power is considered as primary design target. Aprisa’s power-centric optimization offer the option to place low power ahead of other design targets during optimization. This results in higher percentage of low-leakage cells in the designs, and lower power consumption. The Power-centric optimization is available for Adaptive MCMM throughout the flow. In CTS optimization, dynamic power is further reduced through techniques, such as smart clock gate placement and clock gate cloning/decloning.
Full support of both UPF and CPF
Aprisa fully supports both industry standard power specification formats, Unified Power Format (UPF) and Common Power Format (CPF). Hierarchical power specification is flexibly supported by Aprisa’s hierarchical database. Power devices, such as isolation cells, retention cells, level shifters and power gates, are automatically inserted and routed according to the power specification. Intelligent always-on buffer insertion ensures feedthrough buffers through power domains are inserted without unnecessary impact to power and routability. Aprisa also includes a built-in power-spec checker to verify that the power devices are properly inserted according to the power specification.