Aprisa

Interconnect Centric "Precision Optimization"

Floorplanning

Placement and Optimization

Clock Tree Synthesis and Optimization

Timing and Analysis

Multi-corner Multi-mode Analysis

Global Route and Optimization

Detailed Route and Optimization

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Key Benefits

Up To 5x Faster Than The Competition

10-15% Better Timing

Timing That Correlates To Industry Sign Off Tools

Built For Variability

DRC, DFM Clean Designs

Lower Leakage Power

Fewer Buffers Added

Easy To Use

Timing and Analysis

Aprisa includes a next generation timing analysis engine which correlates extremely well to the industry standard sign off tools.

Features

• Very fast, typically 5 minutes per million instances
• Read SDC natively without any translation
• Tight correlation to Primetime-SI and CeltIC
• Native OCV timing analysis
• CRPR Support (clock reconvergence pessimism removal)
• Timing browser (see diagram)