ATopTech Place and Route Receives

TSMC 20nm Phase I Certification

SAN JOSE, CA – May 31, 2012 – ATopTech, the leader in next-generation physical design solutions that address the challenges of designing integrated circuits (ICs), announced today that it has received TSMC Phase I Certification for its Aprisa™ place and route technology.

TSMC certified Aprisa for 20nm design rule manuals (DRMs) and SPICE models. Aprisa supports innovative-patterning compliant place and route, and 20nm DFM rules to facilitate design routability.

 “ATopTech’s mission is to develop best-in-class technology and deliver unsurpassed support for physical implementations,” said Jue-Hsien Chern, CEO of ATopTech, Inc. “The 20nm process requires close collaboration between chip design, process technology and CAD tool development.  It is very rewarding to continue our relationship with TSMC to enable successful 20nm designs.”

“ATopTech has completed Phase I Certification and we look forward to further contributions from them to support TSMC’s advanced technology design ecosystem,” said Suk Lee, Senior Director of Design Infrastructure Marketing at TSMC.  

About Aprisa

Aprisa is a complete place-and-route (P&R engine), including placement, clock tree synthesis, optimization, global routing and detailed routing. The core of the technology is its hierarchical database. Built upon the hierarchical database are common “analysis engines,” such as RC extraction, design rule checking (DRC) engine, and an advanced, extremely fast timing engine to solve the complex timing issues associated with OCV, signal integrity (SI) and multi-corner multi-mode  (MCMM) analysis. Aprisa uses state-of-the-art multi-threading and distributed processing technology to further speed up the process. Because of this advanced architecture, Aprisa delivers predictability and consistency throughout the flow, and faster total turn-around time (TAT) and best quality of results (QoR) for physical design projects.

About ATopTech

ATopTech, Inc. is the technology leader in IC physical design. ATopTech’s technology offers the fastest time to design closure focused on advanced technology nodes. The use of state-of-the-art multi-threading and distributed processing technologies speeds up the design process, resulting in unsurpassed project completion times. For more information, see www.atoptech.com

 

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Aprisa and Apogee are trademarks, and ATopTech is a registered trademark of ATopTech, Inc. Any other trademarks or trade names mentioned are the property of their respective owners.