ATopTech's Aprisa Place and Route Tool Aids Richnex to Increase Product Competitiveness while Reducing the Design Cost
Next-generation multi-channel video decoder chip taped out with smaller area, less power, better timing and shorter turn-around time
SAN JOSE, CA – November 15, 2011 — ATopTech, the leader in next-generation physical design solutions that address the challenges of designing integrated circuits (ICs), has helped Richnex Microelectronics, a subsidiary of Richtek Technology, successfully tape out its next-generation multi-channel video decoder chip with smaller area, less power, better timing and shorter turn-around time. Richnex adopted ATopTech’s Aprisa place and route tool while setting up its internal physical implementation team to increase product competiveness while reducing the design costs.
The Richnex Microelectronics’ new chip is a multi-channel analog video (NTSC/PAL) decoder supporting the advanced 960H/650TVL camera for high quality surveillance applications. Increased video resolution and functionality required a high performance analog front end (AFE) and analog-to-digital converter (ADC) modules, as well as millions of digital gates and SRAM modules, all to be integrated within a very tight schedule.
The combination of ease of setup and ease of use in Aprisa enabled the design to be completed with minimum staffing and training. Aprisa’s focus on high quality of results (QoR) allowed Richnex to achieve area and power savings greater than 10% compared to an earlier similar design as well as ensuring that the design cleared the tapeout sign-off check, including LVS, DRC, electro-migration, and IR drop, with minimum effort. As a result, Richnex experienced a significant savings over previous schedules from the total design time.
"The maturity and overall quality of Aprisa has helped Richnex migrate the backend implementation from design service to in-house team," said Shen Tu, president of Richnex Microelectronics, "The success of this project has increased the overall competitiveness of our product significantly."
“Our technology is designed to benefit both large and small design teams by improving their product values and reducing their overall cost of ownership,” said Jue-Hsien Chern, CEO of Atoptech, Inc, “We are pleased to confirm the value of our technology with this successful collaboration with Richnex.”
Aprisa is a complete place-and-route (P&R engine), including placement, clock tree synthesis, optimization, global routing and detailed routing. The core of the technology is its hierarchical database. Built upon the hierarchical database are common “analysis engines”, such as RC extraction, design rule checking (DRC) engine, and an advanced, extremely fast timing engine to solve the complex timing issues associated with OCV, signal integrity (SI) and multi-corner multi-mode (MCMM) analysis. Aprisa uses state-of-the-art multi-threading and distributed processing technology to further speed up the process. Because of this advanced architecture, Aprisa is able to deliver predictability and consistency throughout the flow, and hence faster total turn-around time (TAT) and best quality of results (QoR) for physical design projects.
ATopTech, Inc. is the technology leader in IC physical design. ATopTech’s technology offers the fastest time to design closure focused on advanced technology nodes. The use of state-of-the-art multi-threading and distributed processing technologies speeds up the design process, resulting in unsurpassed project completion times. For more information, see www.atoptech.com
About Richnex Microelectronics
Richnex Microelectronics is a privately held fabless IC company based in Taiwan, Republic of China. Richnex designs and markets the state-of-the-art mixed-signal ICs for analog video decoding and USB-related applications in markets such as surveillance, digital video recording, analog TV, mobile devices and a range of other high growth areas.
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Michelle Clancy, Cayenne Communication LLC -- 252-940-0981, michelle.clancy@cayennecom