ATopTech’s Physical Design Solutions Delivers Productivity and Quality of
Results to STARC

On time delivery of 45nm design with best productivity, shortest turn-around-time and overall
cost effectiveness

Santa Clara, CA – April 7, 2010 — ATopTech, Inc., the leader in next generation physical
design solutions, today announced that STARC, the leading Japanese Semiconductor Research
Consortium has used ATopTech’s physical design tools to complete a complex hierarchical
design. ATopTech was able to complete the design within the allotted two and a half month
schedule and meet the desired quality of results.

The design used Aprisa for block level design and Apogee for the top-level assembly and timing
closure demonstrating the entire back-end flow within ATopTech’s flow. The twenty-two
million gate design had complex timing requirements, including four corners and five modes for
a total of 20 timing scenarios. Further complicating the design were five different power domains,
which were handled with ease. The final results correlated very closely to sign-off results, run inhouse

“In our most recent SoC design evaluation, ATopTech was able to successfully close timing
while meeting the very aggressive schedule proposed at the start of the project” said Nobuyuki
Nishiguchi, Vice President and General Manager, Development Department, STARC. “We were
highly impressed with the tool’s performance, ease of use and correlation to industry standard
sign-off tools. The improvement in productivity achieved by ATopTech’s tool’s was dramatic.”
“We are pleased that STARC was able to demonstrate ATopTech’s superior quality of results
and best-in-class turn-around time for their recent 45nm design evaluation” said Jue-Hsien Chern,
chief executive officer of ATopTech. “We look forward future technical collaboration with

About ATopTech
ATopTech, Inc., is a technology leader in IC physical design. Its Precision Optimization
technology offers real design closure at 65 nm and below. The company’s first product family,
Aprisa, has extremely accurate correlation to golden sign-off tools, produces design rule check
(DRC)-clean designs, features MCMM optimization at all phases, and offers 10-15 percent better
timing and up to 10 percent less standard cell area than existing tools. The use of state-of-the-art
multi-threading and distributed processing technologies speeds up the design process, resulting
in unsurpassed project completion times. For more information, see

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Aprisa and Apogee are trademarks and ATopTech is a registered trademark of ATopTech, Inc. Any other trademarks or trade names mentioned
are the property of their respective owners.

Editorial Contact:
Michelle Clancy, Cayenne Communication LLC -- 252-940-0981,