ATopTech welcome applications from recent college graduates.
APPLICATION ENGINEER OPENINGS - AUSTIN, TX; CALIF.; EUROPE; INDIA
Candidates with a BS/MS in Electrical Engineering preferred.
The Application Engineer (AE) will be responsible for supporting Aprisa and Apogee physical implementation software products in the ATopTech customer base.
He/She will be accountable for all aspect of physical design flow including floor planning, place and route, clock tree synthesis, timing closure, noise analysis , low power methodologies, and hierarchical design flows for various applications such as wireless, telecommunication, digital video, microprocessors, and networking. He/she will analyze the software issues reported by customers and work with R&D to resolve the issues in a timely manner.
In competitive benchmarks, the AE will need to gather the benchmark data, analyze the metrics required by the customer, and use ATopTech software to produce superior results that exceed customer expectations as well as competitors' results in a limited time frame.
In addition to technical responsibilities, the AE will interface with existing and potential new customers in a consultant role providing deeper insights about ATopTech products and recommending the most optimal methodologies to achieve the customer’s goal while achieving maximum productivity.
Some periodic travel to customer sites will be required, as well as conference calls, tradeshow participation and customer presentations.
To apply submit form
APPLICATION ENGINEER OPENING - SANTA CLARA,CA
Preferred knowledge/experience in the following areas:
Design and implement integrated circuits, and support design flows using Electronic Design Automation tools, including formal verification methodology development, physical implementation methodology development for audio/video processor and mobile processor design at 65nm technology. Conduct technical evaluation and benchmarking of place and route tools at advanced nodes. Accountable for all aspect of physical design flow including floor planning, placement, clock tree synthesis, routing, timing closure, noise analysis, low power, logical equivalence Check's and hierarchical design flows.
Requirements: Bachelor’s degree in Electrical Engineering; 5 years’ experience in job offered or as Services AE (Application Engineer) in support of IC digital tool, IC digital implementation system, and low power flow. The experience must be earned after receipt of bachelor’s degree and be progressively more responsible in nature. Will accept any suitable combination of education, experience or training.
Work site/mail resume to: Atoptech, 2111 Tasman Drive, Santa Clara, CA 95054
To apply submit form
STAFF APPLICATION ENGINEER - SANTA CLARA, CA
Participate at the design, implementation and support of cutting-edge Electronic Design Automation (EDA) tools used to create, simulate, and verify physical design layout of Very Large-Scale Integrated (VLSI) circuits, including synthesis of register transfer level (RTL) to gate level netlist, place and route of the netlist, static timing analysis, and generating Graphic User Interface for Place & Route. Support design flows, accountable for all aspects of physical design flow, deliver technical training and product demos provide technical support, and work closely with R&D team to improve the tools and verify/test fixes, enhancements, and new features.
Requirements: Master’s degree in Electrical Engineering with coursework or experience background in VLSI, computer based simulation and modeling techniques, engineering graphics, synthesis of register transfer level to gate level netlist, graphic user interface for place and route, and automation scripts.
Send resume to: Atoptech, 2111 Tasman Drive, Santa Clara, CA 95054.
Senior R&D (Research and Development) Engineer
Research, design and develop advanced clock tree synthesis technologies, including clock tree synthesis engine design, and optimization of design performance for advanced node processing. Research and design algorithms for timing optimization, including gate level power optimization under timing constraint, voltage scaling algorithm for low power design, linear time complexity current path analysis algorithm. Require: Master’s degree in Computer Science or Computer Engineering and 1 year’s experience in job offered or as Engineer with experience or research background in the development of timing optimization, clock tree synthesis engine design, optimization of design performance, and the algorithms for timing optimization, including gate level power optimization under timing constraint, voltage scaling algorithm for low power design, linear time complexity current path analysis algorithm.
Will accept any suitable combination of education, training, or experience. Work site and mail resume to: Atoptech, Inc., 2111 Tasman Drive, Santa Clara, CA 95054
R&D (Research and Development) Engineer
Research, design and develop the detail router component of P&R (Place and Route) EDA (Electronic Design Automation) tools, including the DFM (Design for Manufacturability) and QoR (Quality of Result) at the latest (such as 20nm node) semiconductor processing. Implement optimization via flow process to improve DFM via rate. Find solutions for difficult place and route issues, such as tricky routing graph problems related to patching rectangles in the routing pattern extraction.
Requirements: Master’s degree in Electrical Engineering with academic or research background in detail router R&D for electronic design automation, including DFM and QoR improvement at 20nm node processing, optimization via flow implementation, and patching rectangles issues in routing pattern extraction.