Company

Careers at ATopTech

Application Engineer - Santa Clara, CA

Application Engineer:

Participate at the design, implementation and support of cutting-edge Electronic Design Automation (EDA) tools used to create, simulate, and verify physical design layout of Very Large-Scale Integrated (VLSI), CMOS and ASIC circuits, including synthesis of register transfer level (RTL) to gate level netlist, place and route of the netlist, static timing analysis, critical paths analysis, clock domain crossing analysis, logic equivalence checking, ECO (Engineering Change Order) implementation, failure mode analysis and quality management; create and modify PERL scripts for tracking RTL progress, data representation and data comparison. Work closely with R&D team to improve the tools and verify/test fixes, enhancements, and new features.

Require: Master's degree in Electrical Engineering with coursework in VLSI Design, CMOS digital circuits, ASIC CMOS Design, Total Quality Management, and Semiconductor Device; 1 year's experience in job offered or as Hardware Engineer with experience in chip design synthesis, static timing analysis, critical paths analysis, clock domain crossing analysis, logic equivalence checking, ECO (Engineering Change Order) implementation, and scripts creation for tracking RTL progress, data representation and data comparison.  Will accept any suitable combination of education, training, and experience.

Work site/mail resume to: Atoptech, Inc., 2111 Tasman Drive, Santa Clara, CA 95054

To apply for this position, please complete the Application Form.

Application Engineer - Austin, Texas; Santa Clara, CA; Taiwan; Korea; India

Preferred knowledge/experience in the following areas:

Design and implement integrated circuits, and support design flows using Electronic Design Automation tools, including formal verification methodology development, physical implementation methodology development for audio/video processor and mobile processor design at 65nm technology. Conduct technical evaluation and benchmarking of place and route tools at advanced nodes. Accountable for all aspect of physical design flow including floor planning, placement, clock tree synthesis, routing, timing closure, noise analysis, low power, logical equivalence Check's and hierarchical design flows.

Requirements: Bachelor's degree in Electrical Engineering; 5 years' experience in job offered or as Services AE (Application Engineer) in support of IC digital tool, IC digital implementation system, and low power flow. The experience must be earned after receipt of bachelor's degree and be progressively more responsible in nature. Will accept any suitable combination of education, experience or training.

Work site/mail resume to: Atoptech, 2111 Tasman Drive, Santa Clara, CA 95054

To apply for this position, please complete the Application Form.

Senior R&D (Research and Development) Engineer -

Participate at the design, implementation and support of Electronic Design Automation (EDA) tools. Develop and support core areas in power analysis and statistic timing analysis for timing optimization, including incremental timing updates, algorithms and data structure development for path search engine, and run time and memory improvement.

Require: Master's degree in Electrical Engineering or Computer Science; 2 years' experience in job offered or as RD (Research Development) Manager. Experience background include timing optimization for EDA tool design, including power analysis, statistic timing analysis, incremental timing updates, path search engine algorithm, and run time and memory improvement. Will accept any suitable combination of education, training, and experience.

Work site/mail resume to: Atoptech, Inc., 2111 Tasman Drive, Santa Clara, CA 95054.

To apply for this position, please complete the Application Form.

R&D (Research and Development) Engineer -

Research, design and develop computer-aided very large scales integrated circuit (VLSI) physical design and verification tools for application specific integrated circuits (ASIC) and system on chip (SoC) design for advanced nodes (nanometers) processing, including the design and implementation of placement and optimization flow, logic synthesis and verification, post-clock-tree-synthesis optimization flow, high-fanout synthesis, cell sizing, leakage power and area optimization.

Require: Master's degree in Electrical Engineering or Electronics Engineering. One year's experience in job offered or as Engineer involved in logic design and verification. Academic or experience background in Computer-aided VLSI system design, system-on-chip verification, physical design for nanometer integrated circuits, and logic synthesis and verification, high-fanout synthesis, flow of placement optimization and post clock tree synthesis optimization. Will accept any suitable combination of education, training or experience.

To apply for this position, please complete the Application Form.

R&D (Research and Development) Engineer -

Research, design and develop the detail router component of P&R (Place and Route) EDA (Electronic Design Automation) tools, including the DFM (Design for Manufacturability) and QoR (Quality of Result) at the latest (such as 20nm node) semiconductor processing. Implement optimization via flow process to improve DFM via rate. Find solutions for difficult place and route issues, such as tricky routing graph problems related to patching rectangles in the routing pattern extraction.

Requirements: Master's degree in Electrical Engineering with academic or research background in detail router R&D for electronic design automation, including DFM and QoR improvement at 20nm node processing, optimization via flow implementation, and patching rectangles issues in routing pattern extraction.

To apply for this position, please complete the Application Form.