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Careers at ATopTech

Staff Application Engineer - Santa Clara, CA

Participate at the design, implementation and support of cutting-edge Electronic Design Automation (EDA) tools used to create, simulate, and verify physical design layout of Very Large-Scale Integrated (VLSI) circuits, including synthesis of register transfer level (RTL) to gate level netlist, place and route of the netlist, static timing analysis, and generating Graphic User Interface for Place & Route. Support design flows, accountable for all aspects of physical design flow, deliver technical training and product demos provide technical support, and work closely with R&D team to improve the tools and verify/test fixes, enhancements, and new features.

Requirements: Master's degree in Electrical Engineering with coursework or experience background in VLSI, computer based simulation and modeling techniques, engineering graphics, synthesis of register transfer level to gate level netlist, graphic user interface for place and route, and automation scripts.
Send resume to: Atoptech, 2111 Tasman Drive, Santa Clara, CA 95054.

To apply for this position, please complete the Application Form.

Senior R&D (Research and Development) Engineer -

Research, design and develop advanced clock tree synthesis technologies, including clock tree synthesis engine design, and optimization of design performance for advanced node processing. Research and design algorithms for timing optimization, including gate level power optimization under timing constraint, voltage scaling algorithm for low power design, linear time complexity current path analysis algorithm.

Require: Master's degree in Computer Science or Computer Engineering and 1 year's experience in job offered or as Engineer with experience or research background in the development of timing optimization, clock tree synthesis engine design, optimization of design performance, and the algorithms for timing optimization, including gate level power optimization under timing constraint, voltage scaling algorithm for low power design, linear time complexity current path analysis algorithm.

Will accept any suitable combination of education, training, or experience. Work site and mail resume to: Atoptech, Inc., 2111 Tasman Drive, Santa Clara, CA 95054

To apply for this position, please complete the Application Form.

R&D (Research and Development) Engineer -

Research, design and develop computer-aided very large scales integrated circuit (VLSI) physical design and verification tools for application specific integrated circuits (ASIC) and system on chip (SoC) design for advanced nodes (nanometers) processing, including the design and implementation of placement and optimization flow, logic synthesis and verification, post-clock-tree-synthesis optimization flow, high-fanout synthesis, cell sizing, leakage power and area optimization.

Require: Master's degree in Electrical Engineering or Electronics Engineering. One year's experience in job offered or as Engineer involved in logic design and verification. Academic or experience background in Computer-aided VLSI system design, system-on-chip verification, physical design for nanometer integrated circuits, and logic synthesis and verification, high-fanout synthesis, flow of placement optimization and post clock tree synthesis optimization. Will accept any suitable combination of education, training or experience.

To apply for this position, please complete the Application Form.

R&D (Research and Development) Engineer -

Research, design and develop the detail router component of P&R (Place and Route) EDA (Electronic Design Automation) tools, including the DFM (Design for Manufacturability) and QoR (Quality of Result) at the latest (such as 20nm node) semiconductor processing. Implement optimization via flow process to improve DFM via rate. Find solutions for difficult place and route issues, such as tricky routing graph problems related to patching rectangles in the routing pattern extraction.

Requirements: Master's degree in Electrical Engineering with academic or research background in detail router R&D for electronic design automation, including DFM and QoR improvement at 20nm node processing, optimization via flow implementation, and patching rectangles issues in routing pattern extraction.

To apply for this position, please complete the Application Form.