Press Releases, Articles and Events
Press Releases
05/30/2013 ATopTech Introduces New Technologies for Aprisa and Apogee Physical Design Solutions at DAC 2013
10/10/2012 ATopTech's Physical Design Solution Included in TSMC 20nm Reference Flow
5/31/2012 ATopTech Place and Route Receives TSMC 20nm Phase I Certification
10/17/2011 Faraday Technology Adopts ATopTech's Aprisa for Physical Implementation at Advance Process Nodes
9/26/2011 NetLogic MicroSystems Selects ATopTech's Next Generation Physical Design Solutions for 28nm Designs
06/06/2011 Extreme DA and ATopTech Extend Cooperation for Timing Sign-off Technology to POCV Analysis
05/31/2011 ATopTech's Aprisa Physical Design Solution Included in TSMC Reference Flow 12.0 for 28nm Designs
05/25/2011 Extreme DA and ATopTech Announce Partnership for Timing Sign-off Closure
03/22/2011 ATopTech Place and Route Engine Included in TSMC's EDA 28nm Routing Qualification Report
02/23/2011 ATopTech Closes 2010 with 70% Growth in Revenue
09/22/10 ATopTech Announces Board of Directors
06/14/10 ATopTech and TSMC Extend Collaboration on Physical Design Solution for 28nm Technology
04/07/10 ATopTech's Physical Design Solutions Delivers Productivity and Quality of Results to STARC
01/19/10 ATopTech's Aprisa Physical Design Solution Qualified by TSMC for 40nm Designs
01/10/10 ATopTech Appoints Jue-Hsien Chern as CEO
07/27/09
ATopTech Introduces Industry.s First
Top-Level Design Tool to Seamlessly Integrate All Hierarchical Functions
with Block-Level Implementation
Adds fully integrated top-down, bottom-up chip planning,
chip assembly, timing closure capabilities to industry-leading portfolio
07/24/09 What to see at DAC, ATopTech recommended by Gary Smith and John Cooley DeepChip
03/31/09 AtopTech, Magma, Apache vs. the Synopsys/Cadence package deals
01/26/09 ATopTech Closes Successful 2008, Reaches Revenue Milestone
Company Sees First 40 nm Design Tape-Out, Expands
Production Tape-Out Count
01/23/08 AtopTech's
Aprisa, Cuts the Physical Design Time
of Sharp's Multimillion-Gate System-on-Chip Design
SoC
designers using Aprisa produced the best quality of results
with very short turn-around time; used flat design methodology which
will be continued on other large SoC designs
Japanese
Version
12/10/07 Pioneers
in Breakthrough IC Design Tools Launch New Company,
Announce Proven Physical Design Product
With
multimillion-dollar revenues, ATopTech is the new face of physical
design
for semiconductors at 90nm and below.
12/10/07 ATopTech Signs
Multi-year, Multi-million Dollar Contract with Broadcom
Aprisa
allows Broadcom to leverage next generation place and route tools for
designing ICs at 65 nm and below
Articles
DeepChip 6/8/10
Apogee floorplanner
Events
TSMC OIP Forum, October 1, 2013
San Jose, CA