ATopTech was founded in 2004 by a team of leading EDA physical design implementation experts expressly to build new technology, from scratch, to deal with these issues design at 90nm and below. Aprisa, the result of these efforts, shipped to customers in December 2006 and has been used successfully in several 65nm tapeouts throughout 2007. Aprisa is currently in active use in several 40nm design efforts.
     Aprisa is a complete netlist-to-GDSII physical design solution, including floorplanning, placement, clock-tree synthesis and optimization, global and detailed routing, and an advanced, extremely fast timing engine to solve the complex timing issues associated with OCV and MCMM analysis. In addition, Aprisa uses state-of-the-art multi-threading and distributed processing technology across the solution to further speed up the process and avoid the exploding runtime issues with modern nanoscale design.

Precision optimization is a new technology that allows Aprisa to do optimization based on much more accurate information than tools in the past. Rather than using very pessimistic models or using a margin based approach, precision optimization is based on very accurate 2.5D parasitic extraction (which is multi-threaded) and SI analysis that is based on near detail route level accuracy. This optimization happens through out the flow, during placement, CTS, and both global route and detailed routing.

Floorplanning

Aprisa provides an easy-to-use floor-planner that enables fast analysis of design hierarchy. Automation of many of the traditionally manual tasks such as manual macro placement and blockage creation helps the designers converge on an optimal floor-plan much faster. Common placement, routing, and timing engines mean good correlation for congestion and timing from floorplanning stage all the way through the final routing stage.

The rich feature set includes:

• Channeled and channel-less floorplans, or a mix of both
• Rectilinear floorplans
• Multiple libraries, and multi-height standard cells
• Parametric multit-hreaded routing for power/ground grid creation
• Automatic placement blockage generator
• Automatic macro placer with grouping and legalization capabilities
• Pin optimization and legalization
• Pad ring placement
• Hierarchical fly line analysis
• Logical hierarchy browser and cross-probing of logical modules to layout

Aprisa´s placement technology is a timing and congestion driven analytical based placer. The placer calls the timing analysis engine frequently to dynamically obtain and update the best net weightings throughout the flow. The placement and optimization engines iterates intelligently between wire-length, routing congestion, area, leakage power and other critical factors to achieve optimal timing, area and power for the block/configuration under consideration. Support includes:

• Complex floorplan / placement constraints including rectilinear regions, multi-height cells, and mixed/overlapping sites,
• Efficient High Fan-out Synthesis
• Intelligent Low power(leakage) optimization
• Area Recovery
• Switching activity aware placement and optimization
• Always-on buffering and retention cell placement
• OCV aware placement
• Useful skew based placement optimization
• Multi-corner and multi-mode placement optimization

Aprisa´s sophisticated CTS engine handles scenarios for complex designs. Optimizing for both area and leakage power, it minimizes the number of buffers. The CTS engine does optimization for skew, minimization of global, local and inter-clock skew and supports useful local skew control for overall timing optimization. In addition, the engine supports:

• Cluster-based clock trees or meshes
• Gated and generated clocks
• Synchronization of generated clock pins
• Automatic clock gate cloning and de-cloning
• Matching of latency targets specified by user for any pins
• Automatic creation of special routing constraints (layer, double width/spacing/via, shielding, etc.)
• Low-Power Clock Tree Synthesis
• Multi-corner and multi-mode clock tree synthesis and clock optimization
• Level-balanced Clock Tree Synthesis
• Route-based clock tree optimization

Additionally, the Clock Tree Browser GUI provides sophisticated features such as cross-probing and editing on the fly such as resizing clock buffers or moving clock buffer/leaf cell to different levels. It provides detailed delay, transition, skew and load information for each node; and can find or highlight any max or min path to calculate local skew.

• Supports unlimited combinations of modes and corners. Any timing options can be put in any scenario, including OCV and link_path_per_instance to name a few.
• Parallel timing analysis distributes scenarios and merges results together for both multi-core CPU and multi-machine topologies. Effects of changes from one scenario to another are tracked so that closure can be achieved.

Aprisa´s fast global route engine can route millions of nets in minutes. The global route includes track assignment so that near detailed route information can be used to generate delays and signal integrity information.

Combined with precision optimization sizing, buffering, and wire spreading can all be looked at concurrently to achieve the best possible solution. All of this is done with MCMM timing. The key is to eliminate the problems such as congestion and signal integrity issues before the detailed route phase. The unique feature of this step is that it is trying to address gross signal-integrity problems during global route stage. This allows more changes than it.s possible during post-route stage. Support includes:

• Iterative fixing of timing and routing to achieve timing closure
• SI aware timing engine enabling fixing the noise violations where they happen i.e. not an after-thought to fix the SI violations.
• Route aware area recovery
• Route aware leakage power optimization
• Metal fill emulation to get accurate prediction of final timing

Aprisa´s detailed router is a hybrid technology. Although the router is gridded, it can route to any off-grid pin when necessary. Unlike other routers which handle lot of DRC as an afterthought, Aprisa router handles all the DRC violations while actually routing the. Coupled with the router is the precision optimization engine to do route based optimization concurrently to fix SI aware timing.

Features

• Multi-threaded engine with near linear performance. An 8 cpu machine will achieve 7-7.5X the performance of a single CPU. Routes 250K instance in about 5 minutes on an 8 CPU machine.
• Supports all 90/65/40nm design rules
• Supports special routing rules such as double wide, double spaced, shielding, double vias, etc.
• Support for DFM issues such as wire-spreading, double-vias, and complex design rules such as end-of-line spacing/extension, min edge, min enclosure, etc. All these rules are honored in-route and not as a post-processing step.
• Electromigration(EM) aware routing and fixing
• Router minimizes unnecessary jogs to achieve shortest wirelength with optimal via count.
• Support for route aware area and power optimization.
• Metal fill emulation to get accurate predicition of final timing.
• No separate step need to fix SI related timing violation; they get concurrently fixed while doing route based optimization