APRISA - Addressing the Crisis in Nanoscale Chip Design

ATopTech was founded in 2004 by a team of leading EDA physical design implementation experts expressly to build new technology, from scratch, to deal with these issues design at 90nm and below. Aprisa, the result of these efforts, shipped to customers in December 2006 and has been used successfully in several 65nm tapeouts throughout 2007. Aprisa is currently in active use in several 40nm design efforts.
     Aprisa is a complete netlist-to-GDSII physical design solution, including floorplanning, placement, clock-tree synthesis and optimization, global and detailed routing, and an advanced, extremely fast timing engine to solve the complex timing issues associated with OCV and MCMM analysis. In addition, Aprisa uses state-of-the-art multi-threading and distributed processing technology across the solution to further speed up the process and avoid the exploding runtime issues with modern nanoscale design.

Interconnect Centric "Precision Optimization"

Precision optimization is a new technology that allows Aprisa to do optimization based on much more accurate information than tools in the past. Rather than using very pessimistic models or using a margin based approach, precision optimization is based on very accurate 2.5D parasitic extraction (which is multi-threaded) and SI analysis that is based on near detail route level accuracy. This optimization happens through out the flow, during placement, CTS, and both global route and detailed routing.

Floorplanning

Aprisa provides an easy-to-use frontend for working out the floorplan of your chip. The initial floorplan may be read in from DEF or created based on user parameters input. Supports:

• Channeled and channel-less floorplans, or a mix of both,
• Rectilinear floorplans,
• Multiple libraries, and multi-height standard cells.
• Parametric route for power/ground grid creation

Macro placement is automatic by default, but Aprisa also enables a designer to manually place macro cells through the graphical user interface (GUI).

Placement and Optimization

Aprisa´s placement technology is a timing and congestion driven analytical based placer. The placer calls the timing analysis engine frequently to dynamically obtain and update the best net weightings throughout the flow. The timing engine iterates intelligently between wire-length, routing congestion, and other critical factors to achieve optimal timing for the block/configuration under consideration. Supports:

• Complex floorplan / placement constraints including rectilinear regions, multi-height cells, and mixed/overlapping sites,
• Efficient High Fan-out Synthesis
• Leakage power optimization
• Area Recovery

Clock Tree Synthesis (CTS) and Optimization

Aprisa´s sophisticated CTS engine handles scenarios for complex designs. Optimizing for both area and leakage power, it minimizes the number of buffers. The CTS engine does optimization for skew, minimization of global skew and inter-clock skew and supports useful local skew control for overall timing optimization. In addition, the engine supports:

• Cluster-based clock trees or meshes
• Gated and generated clocks
• Synchronization of generated clock pins
• Automatic clock gate cloning and de-cloning
• Matching of latency targets specified by user for any pins
• Automatic creation of special routing constraints (layer, double width/spacing/via, shielding, etc.)
• Low-Power Clock Tree Synthesis

Additionally, the Clock Tree Browser GUI provides sophisticated features such as cross-probing and editing on the fly such as resizing clock buffers or moving clock buffer/leaf cell to different levels. It provides detailed delay, transition, skew and load information for each node; and can find or highlight any max or min path to calculate local skew.

Timing Analysis

Aprisa includes a next generation timing analysis engine which correlates extremely well to the industry standard sign off tools.

Features

• Very fast, typically 5 minutes per million instances
• Read SDC natively without any translation
• Tight correlation to Primetime-SI and CeltIC
• Native OCV timing analysis
• CRPR Support (clock reconvergence pessimism removal)
• Timing browser (see diagram)

Multi-corner Multi-mode Analysis (MCMM)

Global Route and Optimization

Aprisa´s fast global route engine can route millions of instances in minutes. The global route includes track assignment so that near detailed route information can be used to generate delays and signal integrity information. Combined with precision optimization sizing, buffering, and wire spreading can all be looked at concurrently to achieve the best solution possible. All of this is done with MCMM timing. The key is to eliminate the problems such as congestion and signal integrity issues before the detailed route phase.

Detailed Route and Optimization

Aprisa´s detailed router is a hybrid technology. Although the router is gridded, it can route to any off-grid pin when necessary.

Features

• Multi-threaded engine with near linear performance. An 8 cpu machine will achieve 7-7.5X the performance of a single CPU. Routes 250K instance in about 5 minutes on an 8 CPU machine.
• Supports all 90/65/45nm design rules
• Supports special routing rules such as double wide, double spaced, shielding, double vias, etc.
• Support for DFM issues such as wire-spreading, double-vias, and complex design rules such as end-of-line spacing/extension, min edge, min enclosure, etc.
• All routing done in-route rather than post processing steps
• Can iterate with precision optimization and MCMM timing engine for optimal results.

The benefits of this approach, that is, a fully "from the ground up" development of a physical-synthesis environment to address the most complex problems in nanoscale chip design, are clear and compelling. Faster design closure, faster project completion, higher performance AND lower power consumption in the final product, and best of all, no surprises, are available to the designer using this state-of-the-art physical synthesis environment.