Atoptech - Tech Briefs

Design teams, attempting to design the next-generation of complex nanoscale (sub-100 nanometer) chips, face several crises. Challenges such as Signal Integrity, OCV, and Multi-Corner Multi Mode timing, and Leakage Power make it much more difficult to achieve design closure (matching physical results such as timing, dies size, and power to those of the design specification), radically increasing design turnaround times and thus hugely escalating the cost. Click fore more...

	Physical Design Tech Briefs Breaking the Bounds of Physical Design in the Nanometer Era Design teams, attempting to design the next-generation of complex nanoscale (sub-100 nanometer) chips, face several crises. Challenges such as Signal Integrity, OCV, and Multi-Corner Multi Mode timing, and Leakage Power make it much more difficult to achieve design closure (matching physical results such as timing, dies size, and power to those of the design specification), radically increasing design turnaround times and thus hugely escalating the cost. Click fore more...